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How to solve the EMI problem in multi-layer PCB design?

Shenzhen Inno Circuit Co.,Ltd | Updated: Jun 20, 2018

How to solve the EMI problem in multi-layer PCB design?

There are many ways to solve EMI problems. Modern EMI suppression methods include using EMI suppression coatings, selecting appropriate EMI suppression parts, and EMI simulation design. This article starts with the most basic PCB layout and discusses the role of PCB stacking in the control of EMI radiation and design techniques.


Power bus


Properly placing a capacitor of appropriate capacity near the IC's power supply pins allows the IC output voltage to jump faster. However, the problem is not the end. Due to the finite frequency response of the capacitor, this does not allow the capacitor to generate the full harmonic power required to cleanly drive the IC output. In addition, the transient voltages formed on the power busbars create a voltage drop across the inductance of the decoupling path. These transient voltages are the main source of common-mode EMI interference. How should we solve these problems?


For ICs on our circuit boards, the power plane around the IC can be considered as an excellent high-frequency capacitor that collects the energy leaked by discrete capacitors that provide high-frequency energy for clean output. In addition, the inductance of the excellent power layer is small, so that the transient signal synthesized by the inductor is also small, thereby reducing common-mode EMI.


Of course, the connection from the power plane to the IC power pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster, and it is best to connect directly to the pad where the IC power pin is located. This is discussed separately.


To control common-mode EMI, the power plane must be conducive to decoupling and have a sufficiently low inductance. This power plane must be a pair of well-designed power planes. Some people may ask, to what extent is it good? The answer to the question depends on the stratification of the power supply, the material between the layers, and the operating frequency (as a function of IC rise time). Typically, the power stratified spacing is 6 mils and the interlayer is FR4 material. The equivalent capacitance per square inch power plane is approximately 75 pF. Obviously, the smaller the interlayer spacing, the greater the capacitance.


Devices with a rise time of 100 to 300 ps. are not many, but according to the current speed of development of ICs, devices with a rise time of 100 to 300 ps will occupy a very high proportion. For circuits with rise times of 100 to 300ps, the 3-mil spacing will no longer apply for most applications. At that time, it was necessary to use a layering technique with an interlayer spacing of less than 1 mil, and to replace the FR4 dielectric material with a material with a high dielectric constant. Ceramic and ceramic plastics can now meet the design requirements for 100 to 300ps rise time circuits.


Although new materials and new methods may be adopted in the future, for today's common 1 to 3ns rise time circuits, 3 to 6 mil interlayers, and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and make the transient signal low enough. Common mode EMI can be lowered very low. The PCB layered stacking design example given in this article will assume a 3 to 6 mil spacing between layers.


Electromagnetic shielding


From the perspective of signal traces, a good slicing strategy should be to place all signal traces in one or several layers, which are next to the power plane or ground plane. For power supplies, a good tiering strategy should be that the power plane is adjacent to the ground plane and the distance between the power plane and the ground plane is as small as possible. This is what we call the “layered” strategy.


PCB board stacking


What kind of stacking strategy helps to shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer, with single or multiple voltages distributed in different parts of the same layer. The case of multiple power planes is discussed later.


4-layer board


There are several potential issues with 4-layer board design. First, a conventional four-layer board with a thickness of 62 mils, even if the signal layer is in the outer layer and the power and ground layers are in the inner layer, the spacing between the power layer and the ground layer is still too large.


If the cost requirement is first, consider the alternatives of the two traditional 4-layer boards below. Both of these solutions can improve EMI suppression performance, but are only suitable for applications where the density of the components on the board is low enough and there is a sufficient area around the component (where the required power copper clad layer is placed).


The first is the preferred solution. The outer layers of the PCB board are ground layers, and the middle two layers are signal/power layers. The power supply on the signal layer is wired with a wide wire, which makes the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From the EMI control point of view, this is the best 4-layer PCB board structure available. The outer layer of the second scheme takes power and ground, and the middle two layers take signals. Compared with the traditional 4-layer board, this scheme has less improvement, and the inter-layer impedance is as poor as the traditional 4-layer board.


If you want to control the impedance of the traces, the above stacking scheme must be very careful to route the traces under the power and ground copper islands. In addition, copper islands on the power or ground should be interconnected as much as possible to ensure DC and low frequency connectivity.


       6-layer board


If the density of the components on the 4-layer board is relatively large, 6-layer board is preferable. However, some laminates in the 6-layer board design do not provide good shielding of the electromagnetic field and have little effect on the transient signal reduction of the power busbar. Two examples are discussed below.


The first example places the power supply and ground on the 2nd and 5th layers respectively. Because of the high impedance of the copper coating on the power supply, it is very unfavorable to control common-mode EMI radiation. However, from the perspective of signal impedance control, this method is very correct.


The second example places the power supply and ground on the 3rd and 4th layers respectively. This design solves the problem of copper resistance of the power supply. Due to poor electromagnetic shielding performance of the 1st and 6th layers, differential mode EMI increases. If the number of signal lines on the two outer layers is the smallest and the trace length is short (less than 1/20 of the highest harmonic wavelength of the signal), this design can solve the problem of differential mode EMI. Copper-filled non-element and non-lead areas on the outer layer and grounding of the copper area (every 1/20 wavelength interval) are particularly good at suppressing differential mode EMI. As mentioned earlier, the copper area is to be connected to the internal ground plane at multiple points.


General Purpose High-Performance 6-Layer Board Design Generally, layers 1 and 6 are laid as ground, and layers 3 and 4 take power and ground. Since there are two layers of dual microstrip signal lines centered between the power plane and the ground plane, the EMI suppression capability is excellent. The disadvantage of this design is that there are only two layers in the trace layer. As mentioned earlier, if the outer traces are short and copper is not routed in the trace area, the same stacking can be achieved using a conventional 6-layer board.


Another 6-layer board layout is signal, ground, signal, power, ground, and signal, which can achieve the environment needed for advanced signal integrity design. The signal layer is adjacent to the ground plane and the power plane is paired with the ground plane. Obviously, the disadvantage is that the layer stack is not balanced.


This usually causes troubles for processing and manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to the power layer or the ground layer after the copper is filled, the board may not be counted as a structurally balanced circuit board. plant. The copper fill area must be connected to power or ground. The distance between the connecting vias is still 1/20 wavelength, not necessarily all the way to connect, but ideally it should be connected.


10-layer board


Due to the very thin insulation layer between the multilayer boards, the resistance between the layer or layer of the 10 or 12 layers is very low. As long as there is no problem with delamination and stacking, excellent signal integrity is completely expected. . It is difficult to manufacture 12-layer boards with a thickness of 62mil, and there are not many manufacturers capable of processing 12-layer boards.


Since the signal layer and the loop layer are always separated by an insulation layer, the scheme of distributing the middle 6 layers to take the signal line in the 10-layer board design is not optimal. In addition, it is important that the signal layer and the loop layer are adjacent, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, and signal.


This design provides a good path for the signal current and its loop current. The appropriate routing strategy is to route layer 1 in the X direction, layer 3 in the Y direction, layer 4 in the X direction, and so on. Intuitively looking at the line, Layer 1 and Layer 3 are a paired layered combination, Layers 4 and 7 are a paired layered combination, Layers 8 and 10 are the last paired layered combination. When it is necessary to change the direction of the trace, the signal line on the first layer should be changed from the “via” to the third layer. In fact, it may not always be possible to do so, but as a design concept, it is still necessary to comply with it.


Similarly, when the signal's trace direction changes, it should be via vias from the 8th and 10th layers or from the 4th layer to the 7th layer. This routing ensures the tightest coupling between the signal's forward path and the loop. For example, if the signal is routed on the first layer and the loop is on the second layer and only on the second layer, then even if the signal on the first layer is transferred to the third layer through the “via”, it The loop is still on the second layer, maintaining low inductance, large capacitance characteristics, and good electromagnetic shielding performance.


If the actual wiring is not the same, what to do? For example, the signal line on the first layer through the via to the 10th layer, then the loop signal has to find the ground plane from the 9th layer, the loop current to find the nearest grounding via (such as The ground pin of a resistor or capacitor. If it happens that there are such holes in the vicinity, it is really lucky. If no such vias are available, the inductance will increase, the capacitance will decrease, and the EMI will increase.


When the signal line must leave the current pair of wiring layers through the vias to other wiring layers, ground vias should be placed next to the vias so that the loop signals can be smoothly returned to the proper ground plane. For Layer 4 and Layer 7 layer combinations, the signal loop will return from either the power plane or the ground plane (ie, 5th or 6th layer) because the capacitive coupling between the power plane and the ground plane is good and the signal is easily transmitted.


Multi-power layer design


If two power planes of the same voltage source need to output large currents, the circuit board factory should be deployed into two sets of power planes and ground planes. In this case, insulation is placed between each pair of power and ground planes. This results in two equal pairs of equal-impedance busbars for the desired bisec- tion current. If the stacking of the power planes causes unequal impedances, the shunting will be uneven, the transient voltage will be much larger, and the EMI will increase dramatically.


If there are multiple supply voltages with different values on the board factory, multiple power supply layers are required accordingly. It is important to remember to create separate paired power and ground planes for different power supplies. In the above two cases, when determining the location of the paired power plane and ground plane in the circuit board factory, keep in mind the manufacturer's requirements for the balanced structure.


to sum up


Since most of the engineers designing the circuit board factory is a traditional printed circuit board factory with a thickness of 62 mils and no blind holes or buried holes, the discussion on layering and stacking in the circuit board plant is limited to this. For circuit board manufacturers that differ greatly in thickness, the layering scheme recommended in this paper may not be ideal. In addition, the process of the circuit board factory with blind holes or buried holes is different, and the layering method in this paper is not applicable.


The thickness, via process, and layer count of the board manufacturer are not critical to the board design. An excellent layered stack is to ensure bypass and decoupling of the power rails and make transients on the power plane or ground plane. The key to minimizing the voltage and shielding the signals from the electromagnetic field of the power supply. Ideally, there should be an insulating isolation layer between the signal trace layer and the loop ground layer. The smaller the pair spacing (or more than one pair) should be, the better. Based on these basic concepts and principles, you can design a circuit board factory that can always meet the design requirements. Now, the rise time of ICs is already very short and will be shorter. The techniques discussed in this paper are indispensable for solving EMI shielding problems.